With the emergence of the laptop computer market, there has been a desire for a new personal computer (PC) that operates at a very low power. Although recently the PC market has been attempting to move to power supply voltages of 3 volts, instead of 5 volts, the focus of reducing power consumption has been centered in the area of when a chip is in a state of little or no activity. Ideally, when a chip is not currently active, it would be beneficial to reduce the power consumption, thereby operating at a lower power than when the chip is constantly drawing power. One method of achieving low power consumption in chips is to employ power management circuits. Power management circuits put the chip into a state that draws little or no current, even though the supply voltage remains coupled to the chip. This state is known as power down. Power management circuits are particularly advantageous to utilize when a chip is not currently active.
One type of prior art power management circuit utilizes external counters to detect activity in the chip. These counters are usually timers keyed to the last access of the chip. These timers act as retriggerable 1-shots, such that when no activity occurs for a predetermined period of time, the chip is allowed to power down. One problem with such a power management scheme is that external control of the power management circuit (i.e., via the counter) is required. When external counters signal that the chip may be put into the powered down state, or mode, an external switch turns off the power. Hence, actually entering the power down mode is externally controlled. Furthermore, these power management circuits are not transparent to software controlling the chip.
In order to put a chip into the power down mode using external circuitry, the clock must be stopped. In order to stop the clock or at least gate the clock, a bus cycle must be launched or a process must be physically executed at the bus cycle level. The absence of any bus cycles being executed (e.g., through default) is an indication that the device can be shut off. Once a bus cycle did occur to a device that was powered off, a mechanism is required for the clock to start. Also, the device would require a means of recovering quickly enough to respond to the cycle. Alternatively, if an access to the powered down or stopped device occurred, the processor might have to execute an instruction twice so that a powered down device would have time to respond. Although these mechanisms work, they are very complicated.
Portable PCs place a high premium on reducing power consumption. The primary mechanism to reduce the active power consumption is to reduce the number of transitions of internal logic, essentially by dividing or stopping the clock. On some PC chips, such as a microprocessor chip, there are numerous functional units. Each functional unit is responsible for performing a different function. At any given time, some of the functional units may be idle and not performing their designated functions, while others are performing their functions. Unnecessary clocking of unused functional units of a processor may contribute to excessive power consumption. For instance, in a processor having a separate floating point unit, when the floating point unit is not executing any floating point instructions, the clocking to the floating point unit causes power to continue to be consumed.
In the prior art, the control of the clock of the floating point functional unit is limited by the minimum operating frequency of the external math co-processor. In other words, shutting off the clock of the floating point unit could not be done independently of the clock of the external math co-processor, and vice versa. Clock control is performed by externally dividing or stopping the floating point clock using software drivers under program or basic input/output system (BIOS) control. In the case of the external math co-processor, stopping the floating point clock cannot be performed independently of stopping the central processing unit (CPU) clock. In the prior art, dividing or stopping the external floating point clock also requires time-out values to be used or programmed. The purpose of these time-out values is to stop the clock after some arbitrary time has elapsed since the last clock to the functional unit. These time-out values are arbitrary. For instance, if 1024 CPU phases have elapsed since the last clock to the functional unit, the clock can be stopped or divided down. Furthermore, when the external clock is stopped, the mechanism to restart the floating point clock requires support from a companion, input/output (I/O) device. In other words, an external I/O device is required to begin the proper clocking of the floating point unit.
In the prior art, to stop the clock, a halt instruction or I/O bus cycle is required. This instruction or I/O bus cycle is used by the external I/O device to generate a stop clock signal back to the CPU. A floating point unit clock cannot be independently or transparently stopped unless the CPU clock is also stopped. The CPU and floating point clock are restarted by an interrupt which breaks the CPU out of the halt condition. The stop clock and interrupt to restart the clock introduce additional latency in the system, due to the logic causing delay in the system and the program execution.
As will be shown, the present invention provides a mechanism that allows on-chip functional units to be automatically stopped when not being used and automatically restarted when being prepared for use. The present invention provides a mechanism for power management which requires no external software control.